Real-World Processors - The 68000

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https://now.ntu.ac.uk/d2l/le/content/716331/viewContent/5356104/View

CPU Performance = Time/Program = Instructions/Program * Cycles/Instructions * Time/Cycle

Instructions Set Architecture (ISA)

Complex Instruction Set Computer (CISC)

Examples

Intel x86

Motorola 68000

Pros/Cons

More cycles per instruction

Less instructions per program

Complex Instructions

Multiple clock cycles per instruction

Different word sizes

Many addressing modes

Hardware must also be complex

Reduced Instruction Set Computer (RISC)

Examples

ARM

MIPS

Pros/Cons

Less cycles per instruction

More Instructions per program

Reduced Instructions

Single clock cycle per instruction

Single word size, reduced set enforced

Indirect addressing is not allowed

Relies more on program size, since less complex

Pipelining is possible

Hardware Implementation

Note: Green stages act as a buffer allowing registers to store information, and allow for pipelining

Motorola 68000 (CISC)

made in 1970s

Havard architecture

Each instructions is broken down into smaller mirco-instructions

8x32bit data accumulator registers (one is a stack pointer)

8x32bit data address registers

24bit address bus and 16bit data bus

16bit instructions, operands may be spread across multiple words

ALU with sub and add capabilities

Operand specification types

Data sizes

MOVE.W is the default

Good for multiplication 2^n

CISC vs RISK illustrations