Storing data

S-R Latch (set reset)

Draw S-R latch

What happens if both inputs are 1

What happens if only one input is 1

What happens if both inputs are 0

IF no prior state - value is inderterminate

ELSE

Draw D latch

Problem is the circuit has no memory any more,

due to when D = 0, the not gate will negate it to a 1

Draw D latch with enable

Problem is when enable is 1,

the data can still be changed "leak",

to solve this you could instantaneously turn off enable but that is hard

Draw a: master slave edge-triggered D Flip-Flop

Note: it is basically two D latches concatenated together

Data is only transferred to the slave when the master makes a enabled/disabled transition

Draw a: master slave edge-triggered D Flip-Flop

Input only stored if clock is 1 and enable is 1