The CPU more detail

ALU

Draw the data path of the ALU performing a adding operation
Explain the image below
What does the ALU need to know?
  • Where to find the values
  • What operations need to be run
  • Stores the data into registers
  • Operation is selected by the control unit
  • Values are selected and operation is performed in 1s or 2s compliment
  • Push output value into output register
  • Result is then moved from output register to the destination register

What does a ALU adder circuit look like (don't draw)

Note: You dont need to know this for the exam, but will need to know its component parts

Look away and draw the decoder unit
What type of circuit is this?

modular - meaning it is made up of smaller parts i.e. decoder, logical unit, adder ...

How you you make it so the ALU can add more then one bit?

Get multiple of them and connect the carry out bit to the carry in bit

Clock

What is the clock in a computer, and what does it serve as?

The clock in a computer emits a series of pulses with fixed delays, and serves to synchronise the components of the system

What is a clock cycle?

This is the 'delay' or time gap between two pulses

What is frequency measured in?

Herts

Registers

What do registers do?

They hold and store data for short periods of time, like the result of a calculation

How are registers implemented?

They are typically implemented using flip-flops

What controls the registers?

ISA - instruction set architecture

Cache

What is cache?

This is a small block of memory that holds data that is likely going to be needed again by the CPU

Specifically what data does it hold?
  1. Data that is currently in use
  1. Data that has just been used
  1. Data that will likely be needed again
Where are the 3 different levels of cache typically located?

L1 and L2 can usually be found on the CPU chip

L3 is usually found off chip

Why are cache faster then memory?
  1. Physically closer to the CPU
  1. Circuit design SRAM

Ways of processing

What is pre-fetching?

Where you fetch data before you need it, in anticipation

What is pipelining?

This is were an instruction is operated on in-sequence however the different stages are in parallel

What is a Superscalar Architecture?
  • This is were you have each pipeline as a separate stage of the pipeline
  • each pipeline is separate from the other pipelines
  • The CPU will execute multiple instructions at once
What are the pros and cons to Superscalar Architecture?

PROS

  • easy to implement

CONS

  • very expensive, for each pipeline to be on a different thread
    • To fix this we could have multiple function units and have a single fetch and store units, however this adds complexity
What is a thread vs a process

Multiple threads will have the same location in memory (basically the same program running in parallel)

Multiple processes will have different locations in memory

What is a multiprocessor system?

This is were there are two or more cores, each core can process a thread, each core has multiple functional units, like superscalar.

What kind of system does a GPU use?

Array processor system and stream processor systems

Data path

What is the data path?

This is the route data will propagate though, as it is processed

What is a combinatorial input?

The input should yield a output immediately, and therefore in theory should be instant

These include the ALU, Number format translators etc

What is a state element?

This is where a register will store data ready for the next cycle to be processed - in this case the state element is the register

Outputs and Inputs only change on the clock edge, when it goes from high to low or low to high

Examples include: registers, Memory, PC

Fetch-Decode-Execute

Describe the fetch decode and execute cycle
  1. Fetch next instruction from memory
  1. PC is incremented by 1
  1. What type of instruction was fetched
  1. If instruction needs a word from memory fetch it, and if needed use a register
  1. Execute the instruction
  1. Goto step 1

Computational time

What is the critical path?

This is the longest path a signal can propagate though, this can limit the clock speed of a CPU

Note: we calculate this though how many gates or transistors the signal passes though

What is circuit depth?

This is how many gates there is from input to output

Moores Law

What is a problem CPU designers face?

The rate that DRAM is progressing is far less than the rate that CPUs are progressing

Draw the CPU Memory gap graph

This is a problem for CPU designers since this is a bottle neck